With rapid evolution of the electronic industry, some major obstacles have surfaced. The need for higher performance, thinness, and thermal performance of the electronic package have pushed the industry search for new packaging technologies. Chip technology has remained mostly in the two-dimensional realm, but an explosion in the number of input-output pins needed for higher performance has led to packaging and assembly challenges, and major heat dissipation and reliability problems.
An initial solution to pin proliferation is the package-on-package platform with perimeter contacts—a solution with numerous benefits, but limited long-term viability due to the relatively small number of pin connections possible between packages, as well as cost and thickness penalties. Another solution is die-stacking with wire bond connections—an otherwise good solution that suffers from yield, thermal, and testing issues as well as performance limitations.
Prior to switching to real 3D chip stacking as an ultimate solution, a 2.5D solution has been proposed in the industry as a bridge between technologies. The state of the art of the 2.5D solution can be typified by use of interposers of thinned, low coefficient-of-thermal-expansion (CTE) wafers made of silicon or glass substrate, with metal plated via holes that are drilled or bored to extend through the substrate between the top and bottom surfaces. Optional redistribution layers (RDLs) may be deposited on either or both sides of a given interposer. The metal plated vias, sometimes called “through-silicon-vias” (TSVs), are often implemented with small diameters and high aspect ratios that present a number of fabrication challenges. For example, drilling tends to be time consuming, and an isolation layer and/or seed layers for the plating are often required. Plating is subject to formation of undesirable voids, lowering yield and lowering structural reliability.